COA Assignment
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Question 1
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A digital computer has
a
common bus system
for 16 registers of 32 bits each. The bus is constructed with
multiplexers.
(i). How many
selection
inputs are there in
each multiplexer?
4 selection input of each multiplexer
(ii). What size of
multiplexers is needed?
16X1 Multiplexer size
(iii). How many
multiplexers are there in the
bus?
32 Multiplexers
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Question 2
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A computer uses a
memory unit
with 256K words
of 32 bits each. A binary instruction code is stored in one word of memory. The
instruction has four parts: an indirect bit, an operation code, a register code
part to specify one of 64 registers, and an address part.
(i). How many bits
are
there in the operation
code, the register code part, and the address part?
Address
bits:
256K
è
28*210
è
218 è
18
18
bits address.
Register Code bits:
64
è 26
è 6
6
bits for register
Operation
code bits:
1
bit for indirect
Indirect
+ opcode + register + address = 32
Opcode
= 32 – 18 – 6 – 1 = 7 bit operation code
(ii). Draw the
instruction
word format and
indicate the number of bits in each part.
|
Indirect
bit
(1bit) |
Operation
code(7bit) |
Register
bits
(6bit) |
Address
bits
(18bit) |
(iii). How
many bits
are there in the data
and address inputs of the memory?
Data 32
bit
Address 18 bit
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Question 3
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Design a 4-bit
combinational
circuit
decrementer using four full-adder circuits
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Question 4
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An output program
resides in
memory starting
from address 2300. It is executed after the computer recognizes an interrupt
when FGO becomes a 1 (while IEN = 1).
a. What
instruction must
be placed at address
1?
The programmer must store a branch instruction that sends the control to an interrupt service routine.
b. What must be
the last
two instructions of
the output program?
Set flags(IEN and R) to 0 and Branch unconditionally jump to 1st address.
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Question 5
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Write a program to
evaluate
the following
arithmetic statement X= [A * (B + C) –D] / (E + F -G)
(i) using a
general
register computer with
three-address instructions,
ADD
R1,B,C
/* R1ßM[B] + M[C] */
MUL
R2,R1,A
/* R2ßR1
* M[A] */
SUB
R3,R2,D
/* R3ß
R2 – M[D] */
ADD
R1,E,F
/*
R1ßM[E] + M[F] */
SUB
R2,R1,G
/* R2ßR1
- M[G] */
DIV
R1,R3,R2
/* R1ßR3/R2
*/
(ii) using an
accumulator
type computer with
one-address instructions,
LOAD
E
/* AC ß
M[E] */
ADD
F
/* AC ß
AC + M[F] */
SUB
G
/* AC ß
AC – M[G] */
STORE T
/* M[T] ß
AC */
LOAD
B
/* AC ß
M[B] */
ADD
C
/* AC ß
AC + M[C] */
MUL
A
/* AC ß
AC*M[A] */
SUB
D
/* AC ß
AC – M[D] */
DIV
T
/* AC ß
AC/M[T] */
STORE X
/*M[X]
ß AC */
(iii) using a
stack
organized computer with
zero-address operation instructions.
PUSH E /* TOS
ß E */
PUSH F /* TOS
ß F */
ADD
/*
TOS ß (E+F) */
PUSH G /* TOS
ß G */
SUB
/*
TOS ß (E + F – G) */
PUSH B /* TOS
ß B */
PUSH C /* TOS
ß C */
ADD
/*
TOS ß (B + C) */
PUSH A /* TOS
ß A */
MUL
/*
TOS ß (B + C)*A */
PUSH D /* TOS
ß D */
SUB
/*
TOS ß [(B + C)*A – D] */
DIV
/*
TOS ß [(B + C)*A – D] / (E
+ F – G)
*/
POP X /* M[X]
ß TOS */
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Question 6
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Write an assembly language subroutine to subtract two numbers. In the calling program, the BSA instruction is followed by the subtrahend and minuend. The difference is returned to the main program in the third location following the BSA instruction.
ORG
100
/Start from 100
BSA
SUB
/branch to
subroutine SUB
HEX
FFFF
/Subtrahend
HEX
FF21
/Minuend
DEC
0
/Difference
HLT
/Program ends
SUB, DEC
0
/BSA address
LDA
SUB
I
/Load Subtrahend
CMA
/Complement
Subtrahend
INC
/Increment
Subtrahend
ISZ
SUB
/Increment SUB
for next address
ADD
SUB I
/Add
minuend
ISZ
SUB
/Increment SUB
for next address
STA
SUB
I
/Storing
subtraction
ISZ
SUB
/Increment SUB
for next address
BUN
SUB I
/branch
unconditionally to go out from subroutine
END
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Question 7
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Explain Booth’s Multiplication algorithm with example.
Flow Chart of Booth’s
Algorithm:
Example:
(-7) * (+3) = (-21)
BR
= -7 è (1001)2
BR’ + 1 è (0111)2
QR
= 3 è (0011)2
|
SC
|
AC
|
QR(Qn-3
Qn-2 Qn-1 Qn) |
Qn+1
|
Comment
|
|
4 |
0000
|
0011
|
0
|
Initialization
|
|
|
0111
|
0011
|
0 |
AC
ß AC +
BR’ + 1
|
|
3 |
0011
|
1001
|
1
|
Ashr
(AC & QR) |
|
2 |
0001
|
1100
|
1
|
Ashr
(AC & QR) |
|
|
1010
|
1100
|
1 |
AC
ß AC +
BR |
|
1 |
1101
|
0110
|
0 |
Ashr
(AC & QR) |
|
0 |
1110
|
1011
|
0 |
Ashr
(AC & QR) |
Multiplication is : AC
QR
(1110
1011) è (-21)10
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Question 8
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Differentiate RISC and CISC architectures.
Characteristics of
CISC:
A large number of
instruction
set
Some instructions were
used
infrequently
(designed only to perform specialized task)
A large variety of
addressing
modes
Variable length
instruction
format
Instructions that
manipulates
operands in
memory
Characteristics of
RISC:
Few instructions
Few addressing modes
Only load and store
instructions access
memory
All other operations
are done
using on processor
registers
Fixed length
instructions
Single cycle execution
of
instructions
The control unit is
hardwired,
not micro-programmed
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Question 9
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Write a short note on
(i)
Daisy Chain
Arbitration (ii) Cache Coherence
Daisy Chain
Arbitration:
Arbitration procedures
service
all processor
requests on the basis of established priorities. A hardware bus priority
resolving technique can be established by means of a serial or parallel
connection of the units requesting control of the system bus. The serial
priority resolving technique is obtained from a daisy-chain connection of bus
arbitration circuits similar to the priority interrupt logic presented.
the daisy-chain
connection of
four arbiters.
It is assumed that each processor has its own bus arbiter logic with
priority-in and priority-out lines. The priority out (PO) of each arbiter is
connected to the priority in (PI) of the next-lower-priority arbiter. The PI of
the highest-priority unit is maintained at a logic 1 value. The
highest-priority unit in the system will always receive access to the system
bus when it requests it. The PO output for a particular arbiter is equal to 1
if its PI input is equal to 1 and the processor associated with the arbiter
logic is not requesting control of the bus. This is the
way that priority is
passed to
the next unit
in the chain. If the processor requests control of the bus and the
corresponding arbiter finds its PI input equal to 1, it sets its PO output to
0. Lower-priority arbiters receive a 0 in PI and generate a 0 in PO. Thus the
processor whose arbiter has a PI = 1 and PO = 0 is the one that is given
control of the system bus.
Cache Coherence:
In a multiprocessor
system,
data
inconsistency may occur among adjacent levels or within the same level of the
memory hierarchy.
In a shared memory
multiprocessor with a
separate cache memory for each processor, it is possible to have many copies of
any one instruction operand: one copy in the main memory and one in each cache
memory. When one copy of an operand is changed, the other copies of the operand
must be changed also.
Example:
Cache and the main
memory may
have
inconsistent copies of the same object.
Suppose there are
three
processors, each
having cache. Suppose the following scenario:-
Processor
1
read X:
obtains 24 from the memory
and caches it.
Processor
2
read X:
obtains 24 from memory and
caches it.
Again,
processor 1 writes as X: 64, It’s
locally cached copy is updated. Now, processor 3 reads X, what value should it
get?
Memory and processor 2
thinks
it is 24 and
processor 1 thinks it is 64.
As multiple processors
operate
in parallel,
and independently multiple caches may possess different copies of the same
memory block, this creates a cache coherence problem.
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Question 10
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Compare following (i) Programmed I/O and Interrupt Initiated I/O (ii) Isolated I/O and Memory Mapped I/O
Programmed I/O and
Interrupt Initiated I/O:
Programmed I/O
operations are
the result of
I/O instructions written in the computer program. Each data item transfer is
initiated by an instruction in the program. Usually, the transfer is to and
from a CPU register and peripheral. Other instructions are needed to transfer
the data to and from CPU and memory. Transferring data under program control
requires constant monitoring of the peripheral by the CPU. Once a data transfer
is initiated, the CPU is required to monitor the interface to see when a
transfer can again be made. It is up to the programmed instructions executed in
the CPU to keep close tabs on everything that is taking place in the interface
unit and the I/O device.
In the programmed I/O
method,
the CPU stays
in a program loop until the I/O unit indicates that it is ready for data
transfer. This is a time-consuming process since it keeps the processor busy
needlessly. It can be avoided by using an interrupt facility and special
commands to inform the interface to issue an interrupt request signal when the
data are available from the device. In the meantime the CPU can proceed to
execute another program. The interface meanwhile keeps monitoring the device.
When the interface determines that the device is ready for data transfer, it
generates an interrupt request to the computer. Upon detecting the external
interrupt signal, the CPU momentarily stops the task it is processing, branches
to a service program to process the I/O transfer, and then returns to the task
it was originally performing.
Isolated I/O and
Memory
Mapped I/O:
The isolated I/O
method
isolates memory and
I/O addresses so that memory address values are not affected by interface
address assignment since each has its own address space
Use the same address space for both memory and I/O. This is the case in computers that employ only one set of read and write signals and do not distinguish between memory and I/O addresses This configuration is referred to as memory-mapped I/O.
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